Gate Driver for SiC MOSFET

Gate Driver for SiC MOSFET Voltage spikes

Authors

  • Uzair Ahmed School of Engineering Asia Pacific University of Technology and Innovation (APU) Kuala Lumpur, Malaysia
  • Raed Abdulla
    raed@staffemail.apu.edu.my
    School of Engineering Asia Pacific University of Technology and Innovation (APU) Kuala Lumpur, Malaysia
  • Freddy Tan Kheng School of Engineering Asia Pacific University of Technology and Innovation (APU) Kuala Lumpur, Malaysia
Vol. 4 No. 3 (2020)
Original Research
January 28, 2026

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SIC Mosfet plays a huge role in power converters and it works under high voltage, high switching frequencies and high temperatures. SiC MOSFETS are widely used in converters are inverters due to their strength but, when connected in half-bridge configurations, there are positive and negative voltage spikes when switching at high frequencies which triggers the lower Mosfet to turn ON and threatens the safe operation of the device. This project focuses on minimizing the voltage spikes by using two capacitors in parallel with resistors which will be able to generate negative voltage without the need of an external power source. This negative voltage will shift the positive and negative voltage spikes below the threshold voltage of the SiC MOSFET so that the device could operate safely. After performing simulation testing using LTspice, it was seen that even at the frequency of 1MHz the gate driver was able keep the voltage spike below the threshold voltage of the SiC MOSFET. The maximum voltage spike was recorded to be 1.3V at 1MHz and 0.08V at 100KHz. As for future recommendations for the enhancement of this project, a much fast switching PNP transistor could enhance the results and if the gate driver is to be used roughly around 100KHz, a diode can be added along the base and emitter of the PNP transistor which would help to create a low impedance path to the negative voltage generated by the capacitors.